Skills in ‘RISC-V’ ISA (Instruction Set Architecture) are vital for students who are keen to work in top companies that design cutting-edge processors based on RISC-V design, which enables a new era of processor design innovation through open standard collaboration

CHENNAI, 1st August 2023: IIT Madras and IIT-M Pravartak Technologies Foundation are calling for registration from students, industry professionals and researchers to take part in the ‘Digital India RISC-V’ Symposium, a one-day event showcasing ‘The future of Electronics in India through the RISC-V pathway.’ It is scheduled to be held on 6th August 2023 at IIT Madras Research Park in Taramani, Chennai.  

IIT Madras is keen to have a lot of participation from students, faculty and working professionals involved in RISC-V designs. This is a good platform to gain insights into the growing RISC-V ecosystem in India. This is an event with limited seats. Registration and participation are free of cost. Registrations are open for the Symposium. Interested can register through the following link - https://pravartak.org.in/dirv_tech_confluence_registration

Shri Rajeev Chandrasekhar, Hon’ble Minister of State in the Ministries of Electronics and Information Technology and Skill Development and Entrepreneurship, Government of India, and Prof. V. Kamakoti, Director, IIT Madras, who developed ‘SHAKTI,’ India’s first indigenously-designed microprocessor based on RISC-V ISA are scheduled to address the event along with other eminent dignitaries.

This Symposium will feature insightful tech talks by esteemed academicians, industry experts, interactive stalls showcasing indigenous RISC-V processors, an engaging hackathon conclusion, and a special investor session.

‘RISC’ stands for ‘Reduced Instruction Set Computer’ contrasted against other prevalent architecture, ‘CISC’ (Complex Instruction Set Computer), ‘V’ stands for fifth generation. The RISC-V project began in 2010. The RISC-V ISA enables a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA aims to deliver a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

The RISC-V foundation was formed in 2015 with IIT Madras being one of the Founder Members. The DIR-V (Digital India RISC-V) Microprocessor Program was launched in 2022 by the GOI, with an overall aim to enable the creation of Microprocessors for the future in India, for the world and achieve industry-grade silicon & Design wins by December 2023.

RISC-V ISA based designs are used by many companies and start-ups. RISC V ISA is open source and free of cost. For academicians, the pedagogy of RISC-V ISA opens up an industry-relevant curriculum with numerous exciting research and applications.

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